SYSPHS12 — Modelica code for Spring corresponding to 'Figure 22' has invalid 'in' and 'out' should probably be 'input' and 'output'

Reporter: Darren Kelly, Webel IT Australia

On p.30 the example Modelica code for Spring corresponding to 'Figure 22: Ports for signal flow in SysML' is invalid, the use of the invalid Modelica keywords in and out is probably a typo:

model Spring
  in Real u;
  out Real y;
end Spring;

Probably the following with input and output is intended :

model Spring
  input Real u;
  output Real y;
end Spring;

Note further, however, that the direct use of input Real and output Real does not correspond well with the SysML concept of Port, as they are not connectable. Compare with the connectable forms:

model Spring
  Modelica.Blocks.Interfaces.RealInput u;
  Modelica.Blocks.Interfaces.RealOutput y;
end Spring;

Where Modelica.Blocks.Interfaces.RealInput is just:

connector RealInput = input Real;

And Modelica.Blocks.Interfaces.RealOutput is just:

connector RealOutput = output Real;

One can get away with using the non-connectable forms when the system is self-contained, such as the SpringMassSys example on p.38, however I suggest this does not correspond well with SysML user expectations and the opportunity could be taken to use the connectable forms throughout most Modelica examples in the spec.