MARTE11 — MARTE-AADL software concept upgrades

The provide a full MARTE AADL alignment, upgrade platform concepts with AADL 1) virtual bus 2) virtual processor concepts

Renumber section 2.4.4 in 2.4.6 Device
Add section 2.4.2 Virtual Processor
A virtual processor represents a logical resource that is capable of scheduling and
executing threads and other virtual processors bound to them. It will be represented as a
MARTE “swSchedulingResource” AND “ProcessingResource” stereotyped UML
Classifier
Add section 2.4.4 Virtual Bus
A virtual bus component represents logical bus abstraction such as a virtual channel or
communication protocol. It will be represented at resource level as a MARTE
“CommunicationMedia” stereotyped UML connection or classifier allocated to the
physical HWBus.
• If the communication media represents a bus, and the clock is the bus speed, "element size" would be the width of the bus, in bits.
• If the communication media represents a layering of protocols, "element size"
would be the frame size of the uppermost protocol.
Disposition: Resolved